Verilog-to-LVS (V2LVS)
Generate the CDL for DigitalCorePads
Layout vs. schematic (LVS)
We want to run LVS with Calibre on the bond-pad level (so no seal ring or dummy fill). Pin labels must be added to the AP level of each pad so that the LVS tool can map the Spice netlist to the layout. They must follow the same naming as ASIC_ALL.sv.
Seal ring assembly
Modify the seal ring template