Seal ring assembly

Modify the seal ring template

Previously, you streamed in a seal ring GDS file. The seal ring is constructed from the following components:

Name	Description	Function	Dimensions (μm2)
CORNER_B	Corner cells	Instantiate at all four corners	178.16 x 178.16
UCSRN	Edge cells	Matrix instantiate depending on length	20 x 2.76
UCSRN_NOVIA	Edge cell overlap	Overlap between UCSRN and CORNER_B	20 x 2.76
N65CHIPCDU2_New	Identifier	Add on all four edges	255.425 x 5.6

If you open the cell SEALRING_1KX1K, you will find a seal ring template. You will need to modify it according to the die dimensions. You will need to have a clearance of a minimum of 5 μm between the pad ring and the seal ring.

Before running APR, you used a PY script at PY_SCRIPTS/pinout/GenChipDim.py which calculates some important values for the seal ring in X and in Y. For example, for the ERASICv1, the PY script prints out the following values for the seal ring:

Distance between SR UCSRN (X,Y): 2460.0, 1960
Distance between SR CORNER_B (X,Y): 2143.68, 1643.68
Number of UCSRN (X,Y): 776, 595

Complete the following steps to modify the seal ring template:

1. Move the north and east instances of UCSRN, CORNER_B, and N65CHIPCDU2_New using the "distance between SR UCSRN" and "distance between SR CORNER_B."
2. For each edge, adjust the number of UCSRN cells tiled together to nearly fill the space between two CORNER_B cells using the "number of UCSRN."
3. For each edge, move one UCSRN_NOVIA cell to fill the gap between one UCSRN cell and one CORNER_B cell.
4. For each edge, ensure that the N65CHIPCDU2_New cell is located 2.2 μm away from the inner edge of the UCSRN cell. Arrange them around the chip so that they are asymmetrical.

Final result (seal ring)

The following image shows the final result of the seal ring for the ERASICv1:

The UCSRN cells are only visible if you zoom in or if you increase the resolution of the display.

Combine ASIC_ALL and seal ring

In the ER_ASIC_Rev1_Tapeout library, create a new cell view called ASIC_Tapeout. Add the ASIC_ALL cell and the SEALRING_1KX1K cell, ensuring they line up properly by placing the seal ring at (0,0) and ASIC_ALL at (25,25) because the UCSRN cell is 20 μm long and the clearance is 5 μm.

Additionally, manually double-check that the clearance on all four edges is 5 μm. The following image shows the clearance measurement on the south edge of the chip:

Final result (ASIC_ALL + seal ring)

The following image shows the final result of ASIC_ALL + seal ring for the ERASICv1: