Pad-level module
Create a module called DigitalCorePads that instantiates the "logical" top-level (DigitalCore), as well as the I/O pads. You will also need a dummy holder for PCORNER that can be included in the RTL folder of DigitalCorePads. Look at previous code for reference.
Synthesis (SYN)
The script that will run synthesis is located at syn/script/syn.tcl. If you run synthesis as is, the pads will be optimized away because they have no logic connections. In syn.tcl, you have to do setdonttouch for all of your pads:
Automatic place and route (APR)
The script that runs APR is located at apr/apr.tcl. You will need to calculate the desired X and Y dimensions of the chip, which are called CoreX and CoreY in apr.tcl.