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Synthesis (SYN)

The script that will run synthesis is located at syn/script/syn.tcl. If you run synthesis as is, the pads will be optimized away because they have no logic connections. In syn.tcl, you have to do set_dont_touch for all of your pads:

syn.tcl
if {$vars(use_pad)} {
	set ALL_PAD [get_cells {PI_* PO_* PTRI_* PP_* *_CORNER}]
	set ALL_PIN [get_nets -of_objects [filter_collection [get_pins -of_objects $ALL_PAD] "name =~ *PAD*"]]
	set_dont_touch $ALL_PAD
	set_dont_touch $ALL_PIN
}
set_dont_touch {VDD VSS DVDD* DVSS*}

Additionally, set each clock to be asynchronous:

syn.tcl
set_clock_groups -asynchronous -group { I_CLK } -group { I_CSPI_CLK }

Before running synthesis, ensure that the clk_list is updated. The chip select timing may need to be handled as well. Look at syn.tcl in DigitalCorePads for reference.